This invention generally relates to a metal-oxide-semiconductor (MOS) capacitor which is, together with a MOS transistor, formed on a semiconductor substrate and to an associated MOS capacitor fabrication method. More particularly, the present invention pertains to a space-saving MOS capacitor.
Small, portable information/communication devices have been developed and commercialized and many of them deal with both digital signals and analog signals. Usually, digital signals and analog signals are processed by separate semiconductor devices because processing of analog signals requires a high-performance capacitor. In circuits which have MOS transistors and which deal with digital signals, a MOS capacitor structure is employed. A MOS capacitor, however, has the disadvantage that its capacitance depends much on the applied voltage. If a MOS capacitor is used to form a part of an analog circuit, this results in causing signals to be distorted badly and, hence, practical applications of the MOS capacitor become difficult.
Japanese Patent Application, published under Pub. No. 61-272963, shows a MOS capacitor. The fabrication of this MOS capacitor is explained. A selected region of a semiconductor substrate is lightly-doped with an impurity, to form a diffusion area of low concentration. Thereafter, the semiconductor substrate is placed in a vacuum at a temperature of 1100 degrees centigrade for about 40 seconds, whereupon implanted impurity atoms present in the vicinity of the surface of the lightly-doped diffusion area are diffused outwardly. As a result, a region of lower concentration in comparison with the lightly-doped diffusion area comes to exist extending from the surface up to a predetermined depth. Subsequently, a thermal oxide layer is formed. A polysilicon layer is formed on the thermal oxide layer. In this way, a MOS capacitor, composed of the polysilicon layer that acts as a top electrode, the lightly-doped diffusion area that acts as a bottom electrode, and the oxide layer that acts as a capacitance section, is fabricated. In accordance with this technique, a region of very low concentration, which extends from the surface of a lightly-doped diffusion area to a predetermined depth, is formed, with a view to holding MOS capacitor leakage current as low as possible.
U.S. Pat. No. 4,877,751 shows a MOS capacitor. This MOS capacitor has an impurity profile such that the impurity concentration at an impurity diffusion area of a semiconductor substrate that acts as a top or bottom electrode for a MOS capacitor, continuously decreases from a surface common to the impurity diffusion area and an oxide layer towards the inside of the semiconductor substrate. In the fabrication of this MOS capacitor, a selected region of a semiconductor substrate is heavily-doped with an impurity, to form a diffusion area having a high concentration of about 10.times.10.sup.20 or more. A thermal oxide layer is formed on the heavily-doped diffusion area. Thereafter, a polysilicon electrode is formed on the thermal oxide layer.
When forming a MOS capacitor that depends less on the applied voltage and a MOS transistor on a semiconductor substrate at the same time, a 2-level polysilicon process has been used. In this 2-level polysilicon process, an oxide layer is placed between two polysilicon layers. Alternatively, a monolevel polysilicon process may be used. In the monolevel polysilicon process, a first oxide layer is placed between a polysilicon layer and a first-level metallization layer and a second oxide layer is placed between the first-level metallization layer and a second-level metallization layer.
In the 2-level polysilicon process, an interlayer film, e.g., a silicon oxide layer, is formed between first- and second-level polysilicon layers, to act as a capacitance section. Although such an interlayer film of silicon oxide may be formed at a step of forming a gate oxide layer for a MOS transistor by thermal-oxidizing a semiconductor substrate, the film thickness of the interlayer film becomes about three to four times the film thickness of the gate oxide layer, because the semiconductor substrate and the heavily-doped polysilicon layer have different oxidation rates.
In the monolevel polysilicon process, a step of forming a polysilicon layer acting as a gate for a MOS transistor, first- and second-level metallization layers, and first and second interlayer dielectric films is utilized. As a result, the first interlayer dielectric film, formed between the polysilicon layer and the first-level metallization layer, has a film thickness of hundreds of nanometers, and the second interlayer dielectric film, formed between the first- and second-level metallization layers, has a film thickness of hundreds of nanometers. The film thickness of the oxide layers (i.e., the capacitance oxide layers) is that thick, which means that a capacitor, made in accordance with a monolevel polysilicon process, is about 50-100 times as large as a capacitor made in accordance with a 2-level polysilicon process.
The 2-level polysilicon process has advantages and disadvantages. While the dependence of the capacitance on the applied voltage is reduced, the number of masks, the number of fabrication steps, the period of processing, and the cost of production all increase in comparison with a conventional monolevel polysilicon process. Additionally, an oxide layer is formed on a polysilicon layer, having a greater film thickness in comparison with a thermal oxide layer grown on a silicon substrate. This is space-consuming and leads to poor capacitor reliability.
Likewise, the monolevel polysilicon process has its advantages and disadvantages. This process achieves a capacitor capable of depending less on the applied voltage; however, it presents the problem that, since an interlayer film of a MOS transistor is used also as a capacitance oxide, the film thickness of the capacitance oxide inevitably increases. This is space-consuming, and larger capacitance requires larger area.
Japanese Patent Application, published under Pub. No. 61-272693, shows a MOS capacitor structure. In accordance with this structure, a diffusion region is formed by a low-dose implantation and a second diffusion region is formed on the first diffusion by a lower-dose implantation. This MOS capacitor structure, however, may present the following drawbacks.
For example, suppose a case where a region is lightly implanted with an n-type impurity to form a lightly-doped diffusion area. In this case, if a voltage applied to a polysilicon electrode is a positive bias, then the polysilicon electrode stores positive electric charges while on the other hand the lightly-doped diffusion area stores negative electric charges. Because of such a light doping, the stored electric charges are not allowed to exist locally on the surface of a semiconductor substrate and space electric charges result. The distribution depth of such space electric charge changes with the applied voltage value, which increases the applied voltage dependence.
On the other hand, if a voltage applied is a negative bias, then the polysilicon electrode stores negative electric charges while the lightly-doped diffusion area stores positive electric charges. As a result, a depletion layer whose depth varies with the applied voltage spreads in the lightly-doped diffusion area. The combined capacitance, C, of the capacitance of the depletion layer, Csc, and the capacitance of the gate insulating layer, Ci, Csc and Ci being in in-series relationship, is given by: C=1/{(1/Ci)+(1/Csc)}. Because the spread of the depletion layer varies with the applied voltage, Csc is voltage-dependent. Additionally, as the depletion layer spreads, the degree of the dependence of Csc upon the applied voltage increases. As a result, the dependence of C upon the applied voltage increases. The capacitance value itself becomes lower. Further, because of the above-described MOS capacitor structure, the spread range of the depletion layer becomes wider.
It is difficult for this prior art MOS capacitor to reduce the dependence of the capacitance upon the applied voltage.
In accordance with the above-noted U.S. Pat. No. 4,877,751, the impurity concentration at an impurity diffusion area surface is about 1.times.10.sup.20 cm.sup.-3, to prevent a depletion layer from widening. Such arrangement makes it possible to reduce the dependence of the capacitance upon the applied voltage. However, a too-high impurity concentration at the diffusion area/dielectric layer interface produces some problems. When a gate oxide layer is simultaneously formed with a dielectric layer for a MOS capacitor by thermal-oxidizing a silicon substrate surface, accelerated oxidization of silicon occurs and the resulting oxide layer becomes thick. For example, FIG. 4 of U.S. Pat. No. 4,877,751 shows an oxide layer having a film thickness of 400-500 nm. Such an oxide layer, which has undergone accelerated oxidization, is thick, in other words, the capacitance per unit area becomes poor, resulting in an increase in the MOS capacitor area. Further, voids are generated in such an oxide layer, which may increase the amount of leakage current therefore decreasing the reliability of gate oxide layers.
As described above, it is hard for the prior art techniques to provide a highly reliable MOS capacitor while at the same time reducing the size of chips. Therefore, the 2-level polysilicon process, which is an expensive process, has been used when mounting MOS capacitors on LSIs.